1. Field of the Invention
The present invention relates to a dynamic random-access memory (DRAM) and a method for testing the DRAM. More particularly, the present invention relates to a DRAM and a method for testing the DRAM in the wafer level burn-in test mode.
2. Description of the Related Art
The wafer level burn-in test is a test of writing data into a DRAM performed when the fabrication of the wafer containing the DRAM is just finished. If a DRAM does not pass its wafer level burn-in test, the DRAM will not be packaged into an individual integrated circuit (IC) in order to reduce manufacturing cost.
When a data of logic one is written into a DRAM, the voltage level of the data signal received by the DRAM is usually the same as that of the power supply voltage of the DRAM. In some circumstances, the wafer level burn-in test would be better if a data signal at a higher voltage level can be written into a DRAM for the test. For example, a surge of high voltage may burst into a DRAM in an event of lightning strike. A wafer level burn-in test using a data voltage higher than the power supply voltage of the DRAM would be very helpful in evaluating the resistance of the DRAM to such events.